The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a pattern for use in steps of manufacturing a semiconductor device including a logic integrated circuit (IC) and also to a method for forming a mask.
Higher performance and integration of a semiconductor integrated circuit (LSI) has been achieved by making a circuit pattern finer. In particular, with respect to a logic LSI, its operation speed (operation frequency) has been improved by reducing a transistor gate length (Lg). With an enlarged chip scale and complicated system, however, a total wiring length within a chip has been abruptly increased, thus resulting in that a speed reduction (interconnect delay) caused by a wiring resistance and capacity governs the entire circuit performance. For the purpose of solving this problem, it becomes important to reduce a chip scale and to suppress the total wiring length by making smaller an interconnect pitch (wiring pitch) (a minimum spacing between centers of adjacent wiring lines or wiring period).
In the circuit formation, optical lithography (reduction projection exposure) is currently used, and its resolution is improved by reducing the wavelength of exposure light and increasing a numerical aperture (NA) of a projection lens. With respect to the above wiring pitch, 0.8-0.5 xcexcm is currently attained with use of a KrF excimer laser exposure apparatus (having a wavelength of 248 nm), and it is considered to be able to attain about 0.4-0.35 xcexcm with use of an ArF excimer laser exposure apparatus (having a wavelength of 193 nm). However, it is expected difficult to realize a smaller wiring pitch than the above level with use of the conventional reduction projection exposure method using far-infrared ray. As a method for realizing a finer pattern, there has been studied an electron beam direct writing (EBDW) method or an X-ray proximity exposure method. In the electron beam direct writing method, however, an enormous amount of time is generally required because individual patterns are sequentially written. In order to solve this problem, there is studied a cell projection method which can collectively transfer certain scales of patterns (e.g., having an about 5 xcexcm square). In this method, however, since the types of settable patterns are restricted, this method is not necessarily effective for a random interconnect pattern of a logic LSI or the like which requires a very large number of types of patterns. (In this connection, it is assumed in this specification that the word xe2x80x9crandomxe2x80x9d is used to mean not iterative or cyclical.) Also there is studied a SCALPEL (SCattering with Angular Limitation Projection Electron-Beam Lithography) method which can scanningly expose a large-area mask. However, its attainable throughput is considered to be about 10 sheets of 8-inch wafers at the most, which corresponds to about {fraction (1/10)} of the throughput by the current optical lithography. The X-ray proximity exposure method, on the other hand, has a problem that it is difficult to realize a mask having a sufficient accuracy.
Meanwhile, as a method for improving a resolution performance without changing an optical system in the optical lithography, a phase-shifting mask method is known. In this method, the resolution of the optical system is remarkably improved over the resolution when a conventional mask is used, by controlling (usually, inverting) the phase of light passed through a specific opening on a mask. There are various types of phase-shifting mask methods, among which an alternating phase-shifting mask method can provide the greatest resolution improving effect. The phase-shifting mask method is discussed, for example, in Handbook of Microlithography, Miromachining, and Microfabrication, Vol.1: Microlithography (SPIE Press, 1997, Bellingham, pp.71-82. The alternating phase-shifting mask method can be easily applied to an alternating pattern as its name implies, but it cannot be necessarily applied to a general pattern of any shape. For example, for Japanese-Character xe2x80x9c⊃xe2x80x9d-shaped pattern or a pattern having three opening patterns are arranged as mutually spaced by a shortest distance, it becomes difficult to obtain phase assignment. An example of a pattern having a difficult phase assignment is shown in FIG. 1.
A method for performing multiple exposure over an identical resist film with use of a plurality of masks including a phase-shifting mask in order to enable transfer of a pattern having an arbitrary shape is filed by the inventors of the present application as Japanese Patent Nos. 2650962 and 2638561. This method is applied, in particular, to processing or the like of a logic LSI gate which requires formation of a highly-thin-line pattern by controlling its line width with a high accuracy. That is, a phase shifter (a region to be inverted in phase on a mask) is arranged so that the phases of openings on both sides of a gate are inverted, whereby a gate pattern can be remarkably improved in its resolution, line width accuracy, depth of focus, etc. However, an edge part of the shifter is transferred as an unnecessary pattern. In order to avoid it, the original design pattern is divided into two mask patterns for multiple exposure. Patterns on each of the above two masks can be automatically generated from the original design pattern through geometrical operations.
A method for generating two phase-shifting masks which can form any pattern based on multiple exposure using a phase retrieval method is suggested by Y. C. Pati, et al (in SPIE: Optical/Laser Microlithography VII, SPIE Vol. 2197 (1994), pp.314-327). This, in principle, proves that any pattern can be realized by the multiple exposure of the two phase-shifting masks.
Also suggested by B. J. Lin (in Japanese Patent Laid-Open Publication: JP-A-8-227140) is a method for dividing any pattern into horizontal and vertical patterns, using the both patterns respectively as a one-dimensional alternating phase-shifting mask, and performing multiple exposure over the both.
Also suggested by Ooi, et al (in Japanese Journal of Applied Physics, Vol. 33 (1994), pp.6774-6778) is a method, for the purpose of applying a phase mask method to a random pattern, for performing phase assignment over a figure at symbolic level and thereafter for performing compaction according to a phase relation between figures to thereby avoid phase conflicts. This method is intended to solve the phase conflicts by relaxing pattern dimensions for the phase conflict parts, which involves change of the design mask pattern itself. In addition, the method is not used to perform multiple exposure over two masks.
As mentioned above, however, we can say that, in the electron beam direct writing method, it is highly difficult to form such a random pattern as a wiring layer or active layer of a logic LSI with a practical throughput.
Meanwhile, it is difficult to apply the alternating phase-shifting mask method to a random pattern. In particular, the scale of a recent logic LSI exceeds such a level as manually designable, and thus the LSI is designed using an automatic place and route method. Accordingly, even formation of the phase-shifting mask phase-shifting mask is required to be carried out for a massive amount of pattern data generated automatically, which cannot be manually done by trial and error impractically. However, since the phase assignment method using the aforementioned phase retrieval method requires a very large amount of computation, it is practically difficult to process the massive amount of data in a practical time, and further a generated mask pattern becomes complex. Thus this method has a problem that the method necessarily pays no consideration to its actual mask manufacturing limit, etc.
The method for performing compaction after phase arrangement at symbolic level goes against the circuit miniaturization because the method relaxes the dimensions of the phase conflict parts.
In the method for dividing a pattern into vertical and horizontal patterns, it is difficult to cope with a general pattern in the random wiring of a logic LSI. For example, when a pattern of FIG. 1 is divided vertically and horizontally, two masks V and H as shown in FIG. 2 are generated. In this case, however, phase conflict between two openings X1 and X2 in the mask H cannot be solved. The known example teaches an idea that, in a similar case, the opening patterns X1 and X2 on the mask are further divided two masks. In this case, however, it is difficult to clearly divide the opening patterns X1 and X2 because the X1 and X2 become an incoherent summation. Further, since a general guideline is not given for it, it becomes difficult to apply this method to a large scale LSI pattern including such a large number of random patterns substantially impossible to be manually processed as mentioned above.
There has not exited so far a general and practical method of applying the alternating phase-shifting mask method to a random interconnect pattern. For this reason, there exist problems that (1) miniaturization of a circuit pattern of a logic LSI as well as reduction of a chip area are undesirably governed by the limits of the wiring pitch in the optical lithography using a conventional mask, and (2) when it is desired to attain a wiring pitch reduction exceeding the limit of the optical lithography using the conventional mask, use of the electron beam direct writing method having a very low throughput is inevitably required.
It is a first object of the present-invention to provide a pattern formation method which can attain a fine alternating wiring pattern exceeding the limit of the prior art method with use of an optical lithography by applying an alternating phase-shifting mask method to a random pattern such as an active layer or wiring layer in a logic LSI.
A second object of the present invention is to provide a general method for generating a mask necessary when an alternating phase-shifting mask method can be applied to the random pattern while eliminating the need for changing a designed pattern itself, and also to provide a computation method for automatically forming a pattern for the mask for a large-scale LSI pattern in a practical time.
A third object of the present invention is to provide a method for manufacturing a semiconductor device (in particular, a logic LSI having a random wiring pattern) having a fine wiring pattern so far considered practically difficult to obtain by a conventional optical lithography, with low cost and high throughput, by using the above pattern formation method and mask. It is also an object to provide a method for manufacturing a high-performance LSI with a reduced chip area and a suppressed interconnect delay, by reducing a wiring pitch of the logic LSI.
(Solving Means)
The above first object is attained, when it is desired to form a desired pattern including broken-line-like figures having a plurality of linear, broken-line-like or branch lines by projecting light passed through a mask onto a resist film formed on a substrate via an optical system to expose the film, by multiple-exposing the resist film with first and second masks including an opening having a grid point corresponding to an end, angular or intersection part of the pattern located substantially in its center. The desired pattern including the broken-line-line figures having linear, broken-line-like or branch lines is preferably a pattern wherein grid points on a predetermined grid are arranged to be connected along the grid. Further, the first and second masks are preferably phase shifter masks.
The first mask is considered to be a phase-shifting mask which has openings with each grid point position of the grid included in the designed pattern located substantially nearly in their centers and wherein the phases of light passed through the adjacent openings spaced by a constant distance are inverted mutually; whereas, the second mask is considered to be a phase-shifting mask which has openings with midpoints between adjacent grid points on a grid in one direction located substantially in their center and wherein the phases of light passed through the adjacent openings spaced by a constant distance are mutually inverted. Further, such a third phase-shifting mask that has openings with midpoints between adjacent grid points of the grid included in the pattern in one direction and a vertical direction located substantially in their center may be multiple-exposed.
Further, the first mask may be a phase-shifting mask which has openings with grid points or nearest neighboring grid points corresponding to ends, corners or intersections of the linear pattern located substantially in their center and wherein the phases of light passed through adjacent openings spaced by a constant distance are mutually inverted; while, the second mask may be a phase-shifting mask which has openings in the form of such linear patterns between the grid points as connected in either one direction of horizontal and vertical directions and wherein the phases of light passed through the openings located within a constant distance in the one direction and in the vertical direction are mutually inverted. When the original pattern includes patterns in both vertical and horizontal directions, such a third phase-shifting mask that has openings in the form of linear patterns as connected between the grid points in a direction vertical to the linear pattern of the second mask and that the phases of light passed through the openings within a constant distance in that direction and in the vertical direction are mutually inverted may be further multiple-exposed.
May be used as the first mask a phase-shifting mask which has openings with grid points corresponding to ends, corners or intersections of the linear pattern or nearest neighboring grid points thereof located substantially in their center and wherein the phases of light passed through the adjacent openings spaced by a constant distance are mutually inverted. May be used as the second mask a phase-shifting mask of a half-tone type which has openings in a region other than the linear pattern or ends of the linear pattern and has a partial transmission region other than the openings through which exposure light is passed as attenuated, and wherein the phase of light passed through the partial transmission region is inverted substantially to the phase of light passed through the openings. Further usable as the first mask is a phase-shifting mask of a half-tone type wherein the above openings are used as they are and the light shielding part is replaced by the partial transmission region similarly to the above second mask. It is preferable that these phase-shifting masks of the half-tone type be exposed by modified illumination.
The above first object is attained, when light passed through a mask is project-exposed onto a resist film formed on a substrate via an optical system to thereby form an arbitrary geometrical pattern on the substrate, by decomposing an existence region of the geometrical pattern with use of a predetermined grid, extracting minimum elements of the grid at intervals of one minimum element in vertical and horizontal directions to divide the entire region decomposed with the grid into four partial regions A, B, C and D, generating opening patterns of dimensions corresponding to a ratio of a common region of the geometrical pattern and each of the minimum elements belonging to the partial regions A, B, C and D occupied within the element in the vicinity of a center of the element, and multiple-exposing at least any two or more of a first phase-shifting mask which has openings generated from said minimum elements belonging to the partial region A, phases of light passed through adjacent ones of said openings within a constant distance being mutually inverted, a second phase-shifting mask which has openings generated from said minimum elements belonging to the partial region B, phases of light passed through adjacent ones of said openings within a constant distance being mutually inverted, a third phase-shifting mask which has openings generated from said minimum elements belonging to the partial region C, phases of light passed through adjacent ones of said openings within a constant distance being mutually inverted, and a fourth phase-shifting mask which has openings generated from said minimum elements belonging to the partial region D, phases of light passed through adjacent ones of said openings in a constant distance being mutually inverted. It is preferable that the arbitrary geometrical pattern be made up of a combination of some of the minimum elements on the grid.
The second object is attained, when a phase-shifting mask pattern is generated by multiple-exposing on a substrate a desired pattern including a designed pattern of grid points on a predetermined grid arranged to connect the grid points along the grid with use of a plurality of phase-shifting masks via an optical system, by generating a first mask pattern including openings corresponding nearly in their centers to positions of the grid points included in the designed pattern and a phase shifter for mutually inverting phases of light passed through adjacent ones of the openings within a constant distance in vertical and horizontal directions, generating a second mask pattern including openings corresponding nearly in their centers to intermediate points between adjacent ones of the grid points included in the designed pattern in the horizontal direction and a phase shifter for mutually inverting phases of light passed through adjacent ones of the openings in vertical and horizontal directions, and generating a third mask pattern including openings corresponding nearly in their centers to intermediate points between adjacent ones of the grid points included in the designed pattern in the vertical direction and a phase shifter for mutually inverting phases of light passed through adjacent ones of the openings within a constant distance in the vertical and horizontal directions.
Alternately the second object is attained by generating a first mask pattern including openings corresponding nearly in their centers to the grid points (which will be generally called the connection nodes) corresponding to ends, corners or intersections in the designed pattern and corresponding to the grid points (which will be called the peripheral nodes) in the vicinity thereof and also including a phase shifter for mutually inverting phases of light passed through adjacent ones of the openings within a constant distance in vertical and horizontal directions, by generating a second mask pattern including such openings as to bury between the connection nodes in the designed pattern in the horizontal direction and including a phase shifter for mutually inverting phases of light passed through adjacent ones of the openings within a constant distance in the vertical direction and by generating a third mask pattern including such openings as to bury between the connection nodes in the designed pattern in the vertical direction and including a phase shifter for mutually inverting phases of light passed through adjacent ones of the openings within a constant distance in the horizontal direction.
Or the second object is attained by generating a first mask pattern which has openings with the connection nodes or peripheral nodes located substantially in their centers and which includes a phase shifter for mutually inverting the phases of light passed through adjacent one of the openings within a constant distance in vertical and horizontal directions, and generating a second mask pattern which has such openings as to bury between the connection nodes respectively in the vertical and horizontal directions in the designed pattern and which includes a half-tone type transmission region for passed as attenuated exposure light through a zone other than the openings and for substantially inverting the phase of the transmitted light to the phase of light passed through the openings.
The third object is attained, when a semiconductor integrated circuit including a wiring pattern having a non-iterative arrangement is manufactured, by generating a plurality of phase-shifting masks for the wiring pattern and by multiple-exposing the phase-shifting masks on an identical resist layer to form the wiring pattern.
(Effects)
In accordance with the present invention, a phase-shifting mask having extracted connection nodes corresponding to ends, corners or intersections of a random interconnect pattern as well as a phase-shifting mask for exposure of the other region are multiple-exposed on an identical resist film via a projection optical system. As a result, since the resolution of an alternating phase-shifting mask method can be realized even for a random pattern such as wiring of a logic LSI or the like, the interconnect pitch of a logic LSI can be reduced by optical lithography, and thus a high-performance LSI having a suppressed interconnect delay (RC delay) can be manufactured with a low cost and a high throughput.